f302d64235
* add verilator package * try to add environment variable and include folder * manually install existing scripts and patch out spack's CXX wrapper * added some comments * make flake8 happy
81 lines
3.7 KiB
Python
81 lines
3.7 KiB
Python
##############################################################################
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# Copyright (c) 2013-2017, Lawrence Livermore National Security, LLC.
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# Produced at the Lawrence Livermore National Laboratory.
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#
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# This file is part of Spack.
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# Created by Todd Gamblin, tgamblin@llnl.gov, All rights reserved.
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# LLNL-CODE-647188
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#
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# For details, see https://github.com/spack/spack
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# Please also see the NOTICE and LICENSE files for our notice and the LGPL.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU Lesser General Public License (as
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# published by the Free Software Foundation) version 2.1, February 1999.
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#
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# This program is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY; without even the IMPLIED WARRANTY OF
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the terms and
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# conditions of the GNU Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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##############################################################################
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from spack import *
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class Verilator(AutotoolsPackage):
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"""Verilator is the fastest free Verilog HDL simulator.
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It compiles synthesizable Verilog (not test-bench code!), plus some PSL,
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SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
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designed for large projects where fast simulation performance is of primary
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concern, and is especially well suited to generate executable models of
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CPUs for embedded software design teams.
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Please do not download this program if you are expecting a full featured
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replacement for NC-Verilog, VCS or another commercial Verilog simulator
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or Verilog compiler for a little project! (Try Icarus instead.) However, if
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you are looking for a path to migrate synthesizable Verilog to C++ or
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SystemC, and writing just a touch of C code and Makefiles doesn't scare you
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off, this is the free Verilog compiler for you.
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Verilator supports the synthesis subset of Verilog, plus initial
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statements, proper blocking/non-blocking assignments, functions, tasks,
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multi-dimensional arrays, and signed numbers. It also supports very simple
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forms of SystemVerilog assertions and coverage analysis. Verilator supports
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the more important Verilog 2005 constructs, and some SystemVerilog
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features, with additional constructs being added as users request them.
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Verilator has been used to simulate many very large multi-million gate
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designs with thousands of modules."""
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homepage = "https://www.veripool.org/projects/verilator"
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url = "https://www.veripool.org/ftp/verilator-3.920.tgz"
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version('3.920', '71de7b9ddb27a72e96ed2a04e5ccf933')
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depends_on('bison')
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depends_on('flex')
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depends_on('perl')
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def setup_environment(self, spack_env, run_env):
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run_env.prepend_path('VERILATOR_ROOT', self.prefix)
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# verilator requires access to its shipped scripts (bin) and include
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# but the standard make doesn't put it in the correct places
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@run_before('install')
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def install_include(self):
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install_tree('include', prefix.include)
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install_tree('bin', prefix.bin)
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# we need to fix the CXX and LINK paths, as they point to the spack
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# wrapper scripts which aren't usable without spack
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@run_after('install')
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def patch_CXX(self):
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filter_file(r'^CXX\s*=.*', 'CXX = {0}'.format(self.compiler.cxx),
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join_path(self.prefix.include, 'verilated.mk'))
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filter_file(r'^LINK\s*=.*', 'LINK = {0}'.format(self.compiler.cxx),
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join_path(self.prefix.include, 'verilated.mk'))
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